1. Field of the Invention
This invention relates generally to radio frequency amplifiers operating in the 0.5 MHz to 100 MHz frequency range and used in Class A, B, and C modes of operation and used in RF power switching amplifiers in Class D, E, F, and S modes of operation in the same frequency range.
2. Description of the Related Art
In the frequency range from approximately 0.5 MHz to 100 MHz, vacuum tubes in various configurations have been used to achieve significant output power levels. For example, power grid electron tube devices are currently employed in applications at these frequencies and can be used in Class A, B, C, D, E, F, and S modes of operation. (A general description of these modes of operation is included in "Solid State Radio Engineering," H. L. Krauss, C. W. Bostian and F. H. Raab; John Wiley and Sons, 1980, Section 14-1 through 14-6 and 16-7.) The vacuum tube devices have performed in a satisfactory manner but are relatively expensive, exhibit a maximum efficiency of approximately 50%-60% and have a limited lifetime. These devices also have narrow band characteristics when compared to semiconductors. More recently, solid state broad band devices have been fabricated that can achieve significant power at levels previously reserved for vacuum tube technology, (e.g., "Power MOSFETs versus Bipolar Transistors"; r.f. design, Nov./Dec. 1981 pages 11-15 by H. O. Cranberg). A variety of problems have prevented the solid state technology from achieving the full potential in this frequency range which the operating characteristics suggest is possible. To achieve useful power levels, the semiconductor devices must typically be operated in parallel. With respect to bipolar transistors, the low input impedances have made the use of these devices, operating in parallel, impractical. Any difference in the input capacitance in the base-emitter junction forward characteristics would result in uneven sharing of input power and unequal power output levels. The power field effect transistor (FET) devices are more tolerant in this respect because of higher input impedances. However, at higher frequencies, the same unequal sharing of input power can exist. When two power field effect transistor devices are operated in parallel, there is a tendency for the two FET devices to break into a spontaneous, relaxation type oscillation when the parasitic capacitances and stray inductances have appropriate values.
To obtain the higher power levels achievable by parallel operation of transistor devices, the implementation of the paralleling technique is provided by isolation between transistor input terminals by means of hybrid couplers, transmission lines etc. For the low impedances associated with the semiconductor devices, these implementations of isolating apparatus between semiconductor devices necessitates impedance transformation to a higher level, typically 50 ohms. The impedance transformation can be accomplished with LC matching networks or wideband radio-frequency transformers. These implementations have limited bandwidth, resulting in degradation at both high and low frequencies. Typically this type of isolation between semiconductor devices is essential only on the input side of the power amplifiers, but can also be implemented on the output side of the amplifiers.
In the case of power field effect transistor devices, the drain terminals of these devices can be coupled in parallel more easily than the collector terminals of bipolar transistor devices because the field effect transistor devices are not subject to certain failures, such as thermal runaway. The FET devices have a higher input impedance than the bipolar devices and lack the forward biased base-emitter junction. The FET gate input terminals can be directly coupled in parallel, provided that the resonance of the stray capacitances and the stray inductances of the devices are within certain values. However, with large devices, these conditions are seldom achieved and the gate terminals must be isolated, typically by apparatus similar to that of the bipolar devices. LC input and output matching networks can be used to transform the low impedance of the input and output terminals to 50 ohms, the common impedance for industrial and communications applications. It is also known to isolate Power FET devices by placing resistors in series with the gate terminals. This technique seriously degrades the frequency response and system performance. Only recently have the solid state devices become available that function usefully at the upper end and of this frequency range.
In the related art, the power output transformer typically has multiple coaxial cables (serving as the secondary winding of the transformer) passing through each ferrite core element (serving as the primary winding of the transformer) and requires the use of DC blocking capacitors for isolation of supply potentials. The DC blocking capacitors are subject to failure and the multiple coaxial cables passing through the ferrite cores increase the difficulty of fabrication.
A need has therefore been felt for a power amplifier unit in which a plurality of amplifying units can be coupled in parallel and can be operated between 0.5 MHz and 100 MHz and utilizing all solid state devices. A need has also been felt for a Class D amplifier device exhibiting 80%-90% efficiency that can utilize these power amplifier units. These power amplifier units can employ FET devices coupled in parallel to achieve output power in the multi-kilowatt range. A need has further been felt for an output transformer that can operate at these high frequencies while combining the output signals from the parallelly coupled power amplifiers and matching the impedance of the output power transistors with the impedance being driven by the transformer.